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A 1.8-V 14-Bit Inverter-Based Incremental Sigma Delta ADC for CMOS Image Sensor | |
Wang, Biao; Zhang, Meng; Cheng, Xu; Feng, Qi![]() | |
发表日期 | 2013 |
ISSN | 2162-7541 |
英文摘要 | This paper presents a 14-bit 100-kHz bandwidth incremental sigma-delta analog-to-digital converter suitable for CMOS image sensors with column-parallel ADCs. By using an inverter instead of an operational trans-conductance amplifier (OTA), the total assumption of modulator is dramatically reduced. To further decrease the power consumption, a body bias inverter is proposed in the inverter, enhancing the current efficiency g(m)/I-DS. Since the decimating filter can be realized with a much simpler structure, a full custom circuit design is applied to the schematic design with a self-timing control cell. The proposed single-ended incremental ADC is designed in 0.18 mu m CMOS technology. The simulation result shows that for a 1.8V supply, 30MHz sampling frequency and 150 oversampling ratio, the power consumption is 122.2 mu W, dynamic range is 85dB and the ENOB is 13.26bit. |
学科领域 | Computer Science; Engineering; Telecommunications |
语种 | 英语 |
WOS研究方向 | Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic ; Telecommunications |
来源期刊 | 2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)
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来源机构 | 中国科学院西北生态环境资源研究院 |
文献类型 | 期刊论文 |
条目标识符 | http://gcip.llas.ac.cn/handle/2XKMVOVA/111710 |
作者单位 | Fudan Univ, Dept Microelect, Shanghai 200433, Peoples R China |
推荐引用方式 GB/T 7714 | Wang, Biao,Zhang, Meng,Cheng, Xu,et al. A 1.8-V 14-Bit Inverter-Based Incremental Sigma Delta ADC for CMOS Image Sensor[J]. 中国科学院西北生态环境资源研究院,2013. |
APA | Wang, Biao,Zhang, Meng,Cheng, Xu,Feng, Qi,&Zeng, Xiaoyang.(2013).A 1.8-V 14-Bit Inverter-Based Incremental Sigma Delta ADC for CMOS Image Sensor.2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON). |
MLA | Wang, Biao,et al."A 1.8-V 14-Bit Inverter-Based Incremental Sigma Delta ADC for CMOS Image Sensor".2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) (2013). |
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